1. Field of the Invention
The present invention relates to an apparatus for adjusting a sampling phase of a digital display and an adjustment method thereof, and more particularly, to an apparatus for adjusting a sampling phase of a digital display in accordance with the number of occurrence of phase shift of video signal during a conversion from analog video signal to digital format, and an adjustment method thereof.
2. Description of the Prior Art
As flat panel display (FPD) such as liquid crystal display (LCD) is in great demand, there are also increasing demands for image processing apparatuses that convert incoming analog video signal into digital format to adaptively use it for display.
For a conversion of analog signal into digital format, a clock signal is generated, and if the phase of the generated clock signal does not correspond with the signal source, image quality deteriorates. Accordingly, the phase of the sampling clock signals needs to be adjusted whenever there occurs a change in signal source.
As an existing method for adjusting the phase of the sampling clock signal, there is a method that adjusts the phase of the sampling clock signal based on a difference of horizontal resolution of pixel data and digital signal.
The sampling phase adjustment apparatus employing the above existing adjustment method is provided with an input level interface into which analog video signal is inputted, an A/D converter for converting incoming analog video signal into digital format, a phase locked loop (PLL) circuit that generates and supplies sampling clock to the A/D converter, a data latch/logic unit that detects number of pixels in an active region where effective video signals exist, and a control unit that controls the PLL by converting the PLL data in accordance with the incoming video signal and the horizontal synchronization signal, and a synchronization signal processing unit that generates information about incoming signal in accordance with the horizontal and the vertical synchronization signals and supplies the generated information to the control unit.
FIG. 1 is a flowchart for illustrating a method for adjusting a sampling clock by detecting number of pixels in the active region with a sampling phase adjusting apparatus.
As shown in FIG. 1, the control unit determines a resolution mode of the incoming video signal in accordance with the horizontal and vertical synchronization signal of the incoming analog video signal in operation S1. Here, the incoming analog video signal is the signal that has been processed at the synchronization signal processing unit. As the resolution mode of the incoming video signal is determined, the control unit sets the PLL by supplying the PLL data corresponding to the resolution mode to the PLL circuit, and thus, the PLL circuit generates a sampling clock at a basic sampling frequency in operation S2. After the A/D conversion at the sampling clock, the data latch/logic unit detects number of pixels in the active region in operation S3. Then through the comparison of the detected number of pixels and reference number of pixels in operation S4, the control unit adjusts the sampling phase to an optimum in accordance with the number of pixels of the active region in operation S5 when the absolute value of the difference equals 1. When the absolute value of the difference is other than ‘1’ in operation S4, operations in S2 and S3 are repeated. After the adjustment of the sampling phase through the operation in S5, the control unit determines whether the detected number of pixels of the active region equals the reference number of pixels in operation S6, and if so, adjusts the horizontal position in accordance with the detected number of pixels of the active region in operation S7. When it is determined that the detected number of pixels of the active region is different from the reference number of pixels in operation S6, the control unit returns to the operation of S2 and re-adjusts the sampling phase.
The above existing method, which adjusts the position of the sampling clock based on the difference between the number of pixels in the active region and the reference number of pixels, have several limitations as follows. That is, the existing method requires computations that are too complex for the capacity of a general microcomputer provided in the digital display to handle. If the resolution of the digital display is increased, it takes a considerable time for the computation, while, if the width of the detected data is reduced to shorten the time for procedures, optimum sampling phase is hardly found.
Meanwhile, there is another method presently available for adjusting the sampling phase. According to this method, whether the beginning and last active data exist in the active video pixel or not is determined based on the horizontal synchronization signal, and the active regions are compared, and if they are correct, optimum sampling phase is determined using the phases of the both active data. However, this method accompanies a problem. That is, if there is no clear difference between the beginning and the last active data as in the case of one dot on/off pattern, while there is no beginning, or last active data in the horizontal direction, or if the phase of the active data is mistakenly determined due to external factors such as noise, error occurs in video data region determination. In brief, the method of determining the median of the beginning and the last phases as an optimum phase is quite prone to errors.